/* CAMLIB  */

#if __STDC__
#define _Cdecl
#else
#define _Cdecl	cdecl
#endif

void  _Cdecl  camo   (int N, int F, int A,	int *D, int *Q, int *X );
void  _Cdecl  cami   (int N, int F, int A,	int *D, int *Q, int *X );
void  _Cdecl  camo24 (int N, int F, int A, long int *D, int *Q, int *X );
void  _Cdecl  cami24 (int N, int F, int A, long int *D, int *Q, int *X );
int   _Cdecl  caml   ( void );
void  _Cdecl  camcl  ( int I );
		      /*  i =  camZ, camQ, camI, camSBIR,
			       camRBIR, camRACL, camRECET */
void  _Cdecl  crate  ( int NC );
		      /*  NC =	1, 2, 3, 4; */
void  _Cdecl  dmaset (int NC, int NOB, int QBL, int unsigned NTR );
		      /*  NOB =  1, 2, 3;  QBL = 0, 1  */
int   _Cdecl  dmao   (int N, int F, int A, char *V );
int   _Cdecl  dmai   (int N, int F, int A, char *V );
		      /*  dmai, dmao = camOk, camNoBus, camErAcl,
				       camDmaHung, camNoXQ  */
unsigned int _Cdecl camcyc (void);


enum camac_reg {	     /* codes for  camcl ( i )		  */
	camZ	    =  1,    /*  Z CYCLE			  */
	camC	    =  2,    /*  C CYCLE			  */
	camI	    =  4,    /*  SET I,CAMAC INHIBIT		  */
	camSBIR     =  8,    /*  SET BUS INHIBIT REG		  */
	camRBIR     =  16,   /*  RESET BUS INHIBIT REG		  */
	camRACL     =  32,   /*  RESET ACL DETECT REG		  */
	camReset    =  64    /*  RESET 6002,ACL & BUS INHIBIT REG */
};

enum camac_errors {		   /*	dmai error return codes  */
	camOk		   =  0,   /*	no error		 */
	camNoBus	   =  1,   /*	no camac bus access	 */
	camErAcl	   =  2,   /*	ACL occurred during DMA  */
	camDmaHung	   =  3,   /*	IBM DMA hung		 */
	camNoXQ 	   =  4    /*	no Q/X after first cycle */
};